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ltc3413 1 3413fc typical application features applications description 3a, 2mhz monolithic synchronous regulator for ddr/qdr memory termination the ltc ? 3413 is a high ef? ciency monolithic synchro- nous step-down dc/dc converter utilizing a constant frequency, current mode architecture. it operates from an input voltage range of 2.25v to 5.5v and provides a regulated output voltage equal to (0.5)v ref while sourcing or sinking up to 3a of output current. an internal voltage divider reduces component count and eliminates the need for external resistors by dividing the reference voltage in half. the internal synchronous power switch with 85m on-resistance increases ef? ciency and eliminates the need for an external schottky diode. switching frequencies up to 2mhz are set by an external resistor. forced-continuous operation in the ltc3413 reduces noise and rf interference. fault protection is provided by an overcurrent comparator that limits output current during both sourcing and sinking operations. adjustable compensation allows the transient response to be optimized over a wide range of loads and output capacitors. figure 1a. high ef? ciency bus termination supply , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178. n high ef? ciency: up to 90% n 3a output current n symmetrical source and sink output current limit n low r ds(on) internal switch: 85m n no schottky diode required n 2.25v to 5.5v input voltage range n v out = v ref /2 n 1% output voltage accuracy n programmable switching frequency: up to 2mhz n power good output voltage monitor n overtemperature protected n available in 16-lead tssop exposed pad package n bus termination: ddr and qdr ? memory, sstl, hstl, ... n notebook computers n distributed power systems pv in sv in pgood sw v ref 22f 4.7m 309k l1: vishay dale ihlp-2525cz-01 0.47 c out : tdk c4532x5r0j107m v in 2.5v c out 100f s 2 3413 f01a v out 1.25v 3a l1 0.47h ltc3413 pgnd run/ss sgnd i th r t v fb 330pf 2200pf 5.11k figure 1b. ef? ciency vs load current load current (a) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 3413 f01b 30 20 10 0 90 100 v in = 2.5v f = 1mhz
ltc3413 2 3413fc pin configuration absolute maximum ratings sv in , pv in supply voltages ......................... ?0.3v to 6v i th , run/ss, v fb , pgood voltages ............ ?0.3v to v in v ref voltage ................................................ ?0.3v to v in sw voltage ................................... ?0.3v to (v in + 0.3v) operating ambient temperature range (note 2) ................................................... ?40c to 85c junction temperature (notes 5, 8)....................... 125c storage temperature range ................. ?65c to 150c lead temperature (soldering, 10 sec) ................ 300c (note 1) fe package 16-lead plastic tssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 sv in pgood i th v fb r t v ref run/ss sgnd pv in sw sw pgnd pgnd sw sw pv in 17 t jmax = 125c, = = ( ) = = ( ) = ( ) = = ( ) = = = = ( )
ltc3413 3 3413fc electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 3.3v, unless otherwise noted. symbol parameter conditions min typ max units f osc switching frequency switching frequency range r osc = 309k (note 6) 0.88 0.30 1.00 1.12 2.00 mhz mhz r pfet r ds(on) of p-channel fet i sw = 300ma 85 110 m r nfet r ds(on) of n-channel fet i sw = 300ma 65 90 m i limit peak current limit 3.8 5.4 a v uvlo undervoltage lockout threshold 1.75 2 2.25 v i lsw sw leakage current v run = 0v, v in = 5.5v (note 7) 0.1 1 a v run run threshold 0.5 0.65 0.8 v note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3413e is guaranteed to meet performance speci? cations from 0c to 70c. speci? cations over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. ltc3413i is guaranteed to meet speci? ed performance from C40c to 85c. note 3: the ltc3413 is tested in a feedback loop that adjusts v fb to achieve a speci? ed error ampli? er output voltage (i th ). note 4: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. typical performance characteristics ef? ciency vs load current ef? ciency vs input voltage load regulation load current (a) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 3413 g01 30 20 10 0 90 100 v in = 2.5v v out = 1.25v t a = 25c v in = 3.3v input voltage (v) 2.5 efficiency (%) 50 60 70 4.0 5.0 3413 g02 40 30 20 3.0 3.5 4.5 80 90 100 5.5 load = 1a load = 3a load = 100ma v out = 1.25v t a = 25c load current (a) 0 C0.30 v out /v out (%) C0.25 C0.20 C0.15 C0.10 0 0.5 1.0 1.5 2.0 3413 g03 2.5 3.0 C0.05 t a = 25c note 5: t j is calculated from the ambient temperature ta and power dissipation p d as follows: ltc3413e: t j = t a + (p d ? 38c/w) note 6: 2mhz operation is guaranteed by design and not production tested. note 7: shutdown current and sw leakage current are only tested during wafer sort. note 8: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability.
ltc3413 4 3413fc typical performance characteristics quiescent current vs input voltage load step transient 20s/div v in = 2.5v v out = 1.25v load step = 0a to 3a output voltage 100mv/div inductor current 1a/div 3413 g11 input voltage (v) 2.0 200 250 350 3.5 4.5 3413 g10 150 100 2.5 3.0 4.0 5.0 5.5 50 0 300 quiescent current (a) t a = 25c frequency vs r osc frequency vs input voltage frequency vs temperature r osc (k) 54 0 frequency (khz) 500 1500 2000 2500 654 754 854 954 4500 3413 g07 1000 154 254 354 454 554 3000 3500 4000 v in = 3.3v t a = 25c input voltage (v) 2.5 990 frequency (khz) 1000 1010 1020 1030 1050 3 3.5 4 4.5 3213 g08 5 5.5 1040 t a = 25c temperature (c) C40 990 frequency (khz) 992 996 998 1000 1010 1004 0 40 60 3413 g09 994 1006 1008 1002 C20 20 80 100 120 v in = 3.3v switch on-resistance vs temperature switch on-resistance vs input voltage switch leakage vs input voltage temperature (c) C40 0 on-resistance (m) 20 40 60 80 040 80 120 3413 g04 100 120 C20 20 60 100 pfet on-resistance nfet on-resistance v in = 3.3v input voltage (v) 2.5 0 on-resistance (m) 20 40 60 80 100 120 3 3.5 4 4.5 3413 g05 5 pfet on-resistance nfet on-resistance t a = 25c input voltage (v) 2.5 0 leakage current (na) 0.5 1.0 1.5 2.0 2.5 3 3.5 4 4.5 3413 g06 5 5.5 pfet nfet t a = 25c
ltc3413 5 3413fc start-up 1ms/div v in = 2.5v v out = 1.25v load = 0.4 output voltage 500mv/div inductor current 1a/div 3413 g13 load step transient 20s/div v in = 2.5v v out = 1.25v load step = 0a to C3a output voltage 100mv/div inductor current 1a/div 3413 g12 typical performance characteristics sv in (pin 1): signal input supply. decouple this pin to sgnd with a capacitor. sv in must be greater or equal to pv in , however, the difference between sv in and pv in must be less than 0.5v. pgood (pin 2): power good output. open-drain logic output that is pulled to ground when the output voltage is not within 10% of regulation point. i th (pin 3): error ampli? er compensation point. the current comparator threshold increases with this control voltage. nominal voltage range for this pin is from 0.2v to 1.4v with 0.6v corresponding to the zero-sense voltage (zero current). v fb (pin 4): feedback pin. receives the feedback voltage from the output. r t (pin 5): oscillator resistor input. connecting a resistor to ground from this pin sets the switching frequency. v ref (pin 6): reference voltage input. the positive input of the internal error ampli? er senses one-half of the volt- age at this pin through a resistor divider. run/ss (pin 7): run control and soft-start input. forcing this pin below 0.5v shuts down the ltc3413. in shutdown all functions are disabled drawing < 1a of supply current. a capacitor to ground from this pin sets the ramp time to full output current. sgnd (pin 8): signal ground. all small-signal components and compensation components should connect to this ground, which in turn connects to pgnd at one point. pv in (pins 9, 16): power input supply. decouple this pin to pgnd with a capacitor. sw (pins 10, 11, 14, 15): switch node connection to inductor. this pin connects to the drains of the internal main and synchronous power mosfet switches. pgnd (pins 12, 13): power ground. connect this pin closely to the (C) terminal of c in and c out . exposed pad (pin 17): should be connected to pcb ground. pin functions
ltc3413 6 3413fc main control loop the ltc3413 is a monolithic, constant frequency, current mode step-down dc/dc converter that is capable of sourc- ing and sinking current at the output. during normal opera- tion, the internal top power switch (p-channel mosfet) is turned on at the beginning of each clock cycle. current in the inductor increases until the current comparator trips and turns off the top power mosfet. the peak inductor current at which the current comparator shuts off the top power switch is controlled by the voltage on the i th pin. the error ampli? er adjusts the voltage on the i th pin by comparing the feedback signal on the v fb pin with a ref- erence voltage that is equal to one-half of the voltage on the v ref pin. when the load current increases, it causes a reduction in the feedback voltage relative to the refer- ence. the error ampli? er raises the i th voltage until the average inductor current matches the new load current. when the top power mosfet shuts off, the synchronous power switch (n-channel mosfet) turns on until either the bottom current limit is reached or the beginning of the next clock cycle. the bottom current limit is set at C7a. the operating frequency is set by an external resistor connected between the r t pin and ground. the switching frequency can range from 300khz to 2mhz. overvoltage and undervoltage comparators will pull the pgood output low if the output voltage comes out of regulation by 10%. in an overvoltage condition, the top power mosfet is turned off and the bottom power mosfet is switched on until either the overvoltage condition clears or the bottom mosfets current limit is reached. dropout operation when the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on-time. further reduction of the supply voltage forces the C + C + C + C + C + 16 10 9 pv in 3 i th 6 v ref 1 8 sv in sgnd 4 v fb pgood sv in pv in slope compensation recovery slope compensation pmos current comparator nmos current comparator oscillator error amplifier logic run run/ss r t 11 14 15 sw sw sw sw 13 7 5 pgnd 3413 bd 12 pgnd 2 1.1v ref 2 0.9v ref 2 functional diagram operation
ltc3413 7 3413fc operation main switch to remain on for more than one cycle until it reaches 100% duty cycle. the output voltage will then be determined by the input voltage minus the voltage drop across the internal p-channel mosfet and the inductor. low supply operation the ltc3413 is designed to operate down to an svin input supply voltage of 2.25v. one important consideration at low input supply voltages is that the r ds(on) of the p-channel and n-channel power switches increases. the user should calculate the power dissipation when the ltc3413 is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. slope compensation and inductor peak current slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at duty cycles greater than 50%. it is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. normally, the maximum inductor peak current is reduced when slope compensation is added. in the ltc3413, however, slope compensation recovery is implemented to keep the maximum inductor peak current constant throughout the range of duty cycles. short-circuit protection when the output is shorted to ground, the inductor cur- rent decays very slowly during a single switching cycle. to prevent current runaway from occurring, a secondary current limit is imposed on the inductor current. if the inductor valley current increases greater than 5a, the top power mosfet will be held off and switching cycles will be skipped until the inductor current is reduced. pre-biased load it is important to sequence the start-up of the ltc3413 prior to any external circuitry that might drive the v out pin. if the v out pin is externally driven to a voltage more than 10% (the ov threshold) above the desired v out voltage, the ltc3413 may enter a latched state where it no longer switches. to avoid this scenario, the user should ensure there is not a pre-biased load during start-up. this can be accomplished by sequencing the ltc3413s run pin before the loads supply. applications information the basic ltc3413 application circuit is shown in figure 1a. external component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by c in and c out . operating frequency selection of the operating frequency is a tradeoff between ef? ciency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequencies improves ef? ciency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. the operating frequency of the ltc3413 is determined by an external resistor that is connected between pin r t and ground. the value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation. r f k osc () 323 10 10 11 .? C _ although frequencies as high as 2mhz are possible, the minimum on-time of the ltc3413 imposes a minimum limit on the operating duty cycle. the minimum on-time is typically 110ns. therefore, the minimum duty cycle is equal to 100 ? 110ns ? f (hz).
ltc3413 8 3413fc applications information inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current i l increases with higher v in or v out and decreases with higher inductance. =
i fl v v v l out out in 1 1 ()( ) C having a lower ripple current reduces the core losses in the inductor, the esr losses in the output capacitors and the output voltage ripple. highest ef? ciency operation is achieved at low frequency with small ripple current. this, however, requires a large inductor. a reasonable starting point for selecting the ripple current is i l = 0.4(i max ). the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below a speci? ed maximum, the inductor value should be chosen according to the following equation: l v fi v v out lmax out in max () () C 1 inductor core selection once the value for l is known, the type of inductor must be selected. actual core loss is independent of core size for a ? xed inductor value, but it is very dependent on the inductance selected. as the inductance increases, core losses decrease. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core losses and are used often at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price versus size requirements and any radiated ? eld/emi requirements. table 1 shows some recommended surface mount induc- tors for ltc3413 applications. table 1. recommended surface mount inductors manufacturer part number value (h) dcr (m) murata lqh55dnr47m01 0.47 13.0 vishay/dale ihlp252czpjr47m01 0.47 4.2 pulse p1166.681t 0.44 6.0 cooper sd20-r47 0.47 20.0 c in and c out selection the input capacitance, c in , is needed to ? lter the trapezoidal wave current at the source of the top mosfet. to prevent large voltage transients from occurring, a low esr input capacitor sized for the maximum rms current should be used. the maximum rms current is given by: ii v v v v rms out max out in in out () C1 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even signi? cant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple
ltc3413 9 3413fc applications information and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by: +
v i esr fc out l out 1 8 the output ripple is highest at maximum input voltage since i l increases with input voltage. multiple capaci- tors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capaci- tors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have signi? cantly higher esr, but can be used in cost-sensitive applications pro- vided that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have excel- lent low esr characteristics but can have a high voltage coef? cient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to signi? cant ringing. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. when choosing the input and output ceramic capacitors, choose the x5r or x7r dielectric formulations. these dielectrics have the best temperature and voltage charac- teristics of all the ceramics for a given value and size. output voltage programming in most applications, v out is connected directly to v fb . the output voltage will be equal to one-half of the volt- age on the v ref pin for this case. v v out ref 2 if a different output voltage relationship is desired, an external resistor divider from v out to v fb can be used. the output voltage will then be set according to the fol- lowing equation: v v r r out ref 2 1 2 1 figure 2. setting the output voltage r2 v out r1 3413 f02 v fb sgnd ltc3413 soft-start the run/ss pin provides a means to shut down the ltc3413 as well as a timer for soft-start. pulling the run/ss pin below 0.5v places the ltc3413 in a low quiescent current shutdown state (i q < 1a). the ltc3413 contains an internal soft-start clamp that gradually raises the clamp on i th after the run/ss pin is pulled above 2v. the full current range becomes available on i th after 1024 switching cycles. if a longer soft-start period is desired, the clamp on i th can be set externally with a resistor and capacitor on the run/ss pin as shown
ltc3413 10 3413fc applications information in figure 1a. the soft-start duration can be calculated by using the following formula: tr vv ss ss in ?c ln v (seconds) ss in C. 18 ef? ciency considerations the ef? ciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the ef? ciency and which change would produce the most improvement. ef? ciency can be expressed as: ef? ciency = 100% - (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: v in quiescent current and i 2 r losses. the v in quiescent current loss dominates the ef? ciency loss at very low load currents whereas the i 2 r loss dominates the ef? ciency loss at medium to high load currents. in a typical ef? ciency plot, the ef? ciency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1. the v in quiescent current is due to two components: the dc bias current as given in the electrical characteris- tics and the internal main switch and synchronous switch gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each time the gate is switched from high to low to high again, a packet of charge dq moves from v in to ground. the resulting dq/dt is the current out of v in that is typically larger than the dc bias current. in continuous mode, i gatechg = f(q t + q b ) where q t and q b are the gate charges of the internal top and bottom switches. both the dc bias and gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages. 2. i 2 r losses are calculated from the resistances of the internal switches, r sw , and external inductor r l . in con- tinuous mode the average output current ? owing through inductor l is chopped between the main switch and the synchronous switch. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on)top )(dc) + (r ds(on)bot )(1 C dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus, to obtain i 2 r losses, simply add r sw to r l and multiply the result by the square of the average output current. other losses including c in and c out esr dissipative losses and inductor core losses generally account for less than 2% of the total loss. thermal considerations in most applications, the ltc3413 does not dissipate much heat due to its high ef? ciency. but, in applications where the ltc3413 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. if the junction temperature reaches approximately 150c, both power switches will be turned off and the sw node will become high impedance. to avoid the ltc3413 from exceeding the maximum junc- tion temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the temperature rise is given by: t r = (p d )( ja ) where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient temperature.
ltc3413 11 3413fc applications information the junction temperature, t j , is given by: t j = t a + t r where t a is the ambient temperature. as an example, consider the ltc3413 in dropout at an input voltage of 3.3v, a load current of 3a and an ambi- ent temperature of 70c. from the typical performance graph of switch resistance, the r ds(on) of the p-channel switch at 70c is approximately 97m. therefore, power dissipated by the part is: p d = (i load 2 )(r ds(on) ) = (3a) 2 (97m) = 0.87w for the tssop package, the ja is 38c/w. thus the junc- tion temperature of the regulator is: t j = 70c + (0.87w)(38c/w) = 103c which is below the maximum junction temperature of 125c. note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (r ds(on) ). checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load (esr), where esr is the effective series resistance of c out . i load also begins to charge or dis- charge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the i th pin external components and output capacitor shown in figure 1a will provide adequate compensation for most applications. output voltage tracking of v ref for applications in which the v ref pin is connected to the v in pin, the output voltage will be equal to one-half of the voltage on the v in pin. because the output voltage will track the input voltage, any disturbance on v in will appear on v out . for example, a load step transient could cause the input voltage to drop if there is insuf? cient bulk capacitance at the v in pin. the corresponding drop in the output voltage during the load step transient is caused by the v out tracking of v in and should not be confused with poor load regulation. design example as a design example, consider using the ltc3413 in an application with the following speci? cations: v in = 2.5v, v out = 1.25v, i out(max) = 3a, f = 1mhz. first, calculate the timing resistor: rkk osc 323 10 110 10 313 11 6 .? ? C use a standard value of 309k. next, calculate the inductor value for about 40% ripple current: l v mhz a v v 125 112 1 125 25 04 . ?. C . . .7 7 h using a 0.47h inductor results in a maximum ripple current of: =

i v mhz h v v l 125 1047 1 125 25 . ?. C . . 133 .a c out will be selected based on the esr that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. for this design, two 100f ceramic capacitors will be used. c in should be sized for a maximum current rating of: ia v v v v a rms rms 3 125 25 25 125 115 . . . . C. decoupling the pv in pins with two 100f capacitors is adequate for most applications. connect the v ref pin directly to sv in . connecting the v fb pin directly to v out will set the output voltage equal to one-half of the volt- age on the v ref pin. the complete circuit for this design example is illustrated in figure 3.
ltc3413 12 3413fc applications information 3. keep the switching node, sw, away from all sensitive small-signal nodes. 4. flood all unused areas on all layers with copper. flood- ing with copper will reduce the temperature rise of power components. you can connect the copper areas to any dc net (pv in , sv in , v out , pgnd, sgnd or any other dc rail in your system). 5. connect the v fb pin directly to the v out pin. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3413. check the following in your layout. 1. a ground plane is recommended. if a ground plane layer is not used, the signal and power grounds should be segregated with all small-signal components returning to the sgnd pin at one point which is then connected to the pgnd pin close to the ltc3413. 2. connect the (+) terminal of the input capacitor(s), c in , as close as possible to the pv in pin. this capacitor provides the ac current into the internal power mosfets. r pg 100k r ith 5.11k r osc 309k *vishay dale ihlp-2525cz-01 0.47h **tdk c4532x5r0j107m r ss 4.7m c ss 330pf x7r c ith 2200pf x7r c c 100pf pgood sv in pgood i th v fb r t v ref run/ss sgnd pv in sw swv fb pgnd pgnd sw sw pv in 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc3413 l1* 0.47h c in1 ** 100f c in2 ** 100f c out ** 100f s 2 gnd 3413 f03 v out 1.25v 3a v in 2.5v figure 3. one-half v ref , 3a ddr memory termination supply at 1mhz (ef? ciency curve is shown in figure 1b)
ltc3413 13 3413fc applications information (4a) top layer (4b) bottom layer (4c) pcb photo figure 4. ltc3413 layout design
ltc3413 14 3413fc typical applications r pg 100k r ith 5.11k r osc 309k *vishay dale ihlp-2525cz-01 0.47h **tdk c4532x5r0j107m r ss 4.7m c ss 330pf x7r c ith 2200pf x7r c c 100pf pgood 2.5v sv in pgood i th v fb r t v ref run/ss sgnd pv in sw swv fb pgnd pgnd sw sw pv in 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc3413 l1* 0.47h c in1 ** 100f c in2 ** 100f c out ** 100f s 2 3413 ta01 v out 1.25v 3a v in 3.3v gnd load current (a) 0.01 efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 0.1 1 10 1.25v, 3a ddr memory termination supply at 1mhz ef? ciency vs load current, v in = 3.3v, v out = 1.25v, f = 1mhz
ltc3413 15 3413fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description fe package 16-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663, exposed pad variation ba) fe16 (ba) tssop 0204 0.09 C 0.20 (.0035 C .0079) 0 C 8 0.25 ref 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 134 5 6 7 8 10 9 4.90 C 5.10* (.193 C .201) 16 1514 13 12 11 1.10 (.0433) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 2.74 (.108) 2.74 (.108) 0.195 C 0.30 (.0077 C .0118) typ 2 millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in recommended solder pad layout 3. drawing not to scale 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 2.74 (.108) 2.74 (.108) see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc
ltc3413 16 3413fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com linear technology corporation 2008 lt 0708 rev c ? printed in usa related parts typical application part number description comments ltc3406 600ma, (i out ) 1.5mhz synchronous step-down regulator v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 20a, thinsot ltc3407 dual 600ma, (i out ) 1.5mhz, synchronous step-down regulator v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40a, ms10e ltc3411 1.25a, (i out ) 4mhz, monolithic synchronous step-down regulator v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 60a, ms, dfn-10 ltc3412 2.5a, (i out ) 4mhz, monolithic synchronous step-down regulator v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 60a, tssop-16 ltc3414 4a, (i out ) 4mhz, monolithic synchronous step-down regulator v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 64a, tssop-20e ltc3713 low input voltage, no r sense ? synchronous controller v in : 1.5v to 10v, v out(min) = 0.8v, ssop-24 ltc3717 no r sense controller for ddr memory termination v in : 5v to 36v, v out(min) = 0.8v, ssop-24 ltc3718 low input voltage, no r sense controller for ddr memory termination v in : 1.5v to 10v, v out(min) = 0.8v, ssop-24 no r sense is a trademark of linear technology corporation. r pg 100k r ith 10k r osc 309k *vishay dale ihlp-2525cz-01 0.47h **tdk c4532x5r0j107m ? taiyo yuden jmk325bj226mm ?? sanyo poscap 4tpd470m r ss 4.7m c ss 330pf x7r c ith 2200pf x7r c c 100pf pgood 1.5v sv in pgood i th v fb r t v ref run/ss sgnd pv in sw swv fb pgnd pgnd sw sw pv in 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc3413 l1* 0.47h c in1 ** 100f c in2 ** 100f c out1 ? 22f c out2 ?? 470f gnd 3413 ta02 v out 0.75v 3a v in 3.3v + 3.3v to 0.75v, 3a hstl application

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